The present invention relates to a vertical MOSFET used as a switching device or the like.
FIGS. 7 and 8 show a conventional power MOSFET (Japanese patent provisional publication No. 59-98557). The vertical MOSFET device shown in FIG. 7 is formed on and in a semiconductor substrate having a highly doped N.sup.+ bottom layer 21, a lightly doped N top layer 23 which functions substantially as a drain, and an intermediate N.sup.* layer 22 formed between the bottom and top layers 21 and 23. A plurality of P-type channel regions 24 are formed in the N top substrate layer 23. FIG. 7 shows only one of the regions 24. A P.sup.* well region 25 is formed in a central portion of each channel region 24. Each of the P.sup.* well regions 25 is made deeper than the P channel regions 24. Each well region 25 extends deeply from the top surface of the substrate into the N top layer 23, and reaches the N.sup.* intermediate layer 22, so that a PN junction 26 is formed between the bottom of the P.sup.* well region 25 and the N.sup.* intermediate layer 22. This PN junction 26 functions as a clamping diode 27 for preventing the potential of the drain from exceeding a predetermined value.
An N.sup.+ source region 28 is formed in each P channel region 24. Above the P channel region 24 between the N.sup.+ source region 28 and the N top layer 23, there is formed an insulated gate electrode 30 for inducing a channel 24a in the P channel region along the top surface of the substrate. The gate electrode 30 is insulated by a gate insulating film 29.
In FIG. 7, there are further shown a P.sup.+ base region 31, a PSG insulating interlayer 32, a topside source electrode 33, and a drain electrode 34 formed on the bottom of the N.sup.+ bottom layer 21. The source electrode 33 is connected with the source region 28, and further connected with the P channel region 24 and the P.sup.* well region 25 through the P.sup.+ base region 31.
When a positive voltage of a predetermined magnitude is applied to the drain electrode 34 and a gate voltage above a threshold voltage is applied to the gate electrode 30, then the channel 24a becomes conductive, and allows a current to flow from the drain electrode 34 to the source electrode 33. In the vertical MOSFET having such a structure, there is formed a parasitic NPN bipolar transistor 35 which has an emitter formed by the N.sup.+ source region 28, a base formed by the P channel region 24, and a collector formed by the N top substrate layer 23. In the P channel region 24 and the P.sup.+ base region 31, there are formed base resistances Rb.sub.1, Rb.sub.2 and Rb.sub.3 of the transistor 35. In this structure shown in FIG. 7, the base resistances Rb.sub.2 and Rb.sub.3 are lowered by formation of the highly doped P.sup.+ base region 31. However, the structure of FIG. 7 does not have any means for lowering the resistance Rb.sub.1.
Therefore, the resistance Rb.sub.1 increases the possibility of second breakdown. When, for example, the vertical MOSFET is used as a switching device for an inductive load, a high surge voltage applied between the drain and source during turn-off tends to cause a breakdown of the junction between the P channel region 24 and the N substrate layer 23. The resulting breakdown current can easily turn on the bipolar transistor 35 by flowing through the resistance Rb.sub.1, with the result of second breakdown and thermal destruction of the device.
The vertical MOSFET device of FIG. 7 is designed to decrease such an undesired tendency toward permanent destruction of the device by forming the clamping diode 27 between the P.sup.* well region 25 and the N.sup.* intermediate layer 22. This clamping diode 27 is turned on by application of a high surge voltage between the drain and source, and functions to prevent the potential of the N substrate layer 23 from exceeding a predetermined value. In this way, the clamping diode 27 decreases the tendency to second breakdown and thermal destruction by preventing breakdown of the junction between the N layer 23 and the P channel region 24.
In this conventional device, however, the P.sup.* well region 25 is made deeper than the P channel region 24 so that the N.sup.* intermediate substrate layer 22 is reached by the P.sup.* well region 25, and the clamping diode 27 is formed by the PN junction 26 between the P.sup.* well region 25 and the N.sup.* intermediate layer 22.
Especially when this vertical MOSFET is used as a power switching device, it is desirable to make the clamping voltage of the clamping diode 27, that is, the upper limit of the drain voltage, as high as possible within the range in which a breakdown at the P channel region 24 can be prevented.
In order to increase the clamping voltage of the clamping diode 27, it is necessary to decrease the impurity concentrations of the P.sup.* well region 25 and the N.sup.* intermediate layer 22, and to make the P.sup.* well region 25 sufficiently deep to ensure a depletion layer whose width is increased by decrease of the doping levels of the P.sup.* well region 25 and the N.sup.* layer 22.
However, the diffusion step to deepen the P channel region 25 entails increase in the lateral diffusion, which results in a larger cell size and a higher on resistance.